Xilinx takes RFSoCs to the next level for 5G, cable and radar
Based on 16nm UltraScale+ MPSoC architecture, the All Programmable RFSoCs monolithically integrate RF data converters for up to 50-75 percent system power and footprint reduction, and soft-decision Forward Error Correction (SD-FEC) cores to meet 5G and DOCSIS 3.1 standards.
Zynq RFSoCs combine RF data converters and SD-FEC cores with high performance 16nm UltraScale+ programmable logic and ARM® multi-processing system to create a comprehensive analog-to-digital signal chain. While RF to digital signal conditioning and processing is typically segmented into stand-alone subsystems, these RFSoCs bring analog, digital, and embedded software design onto a single monolithic device for system robustness.
The All-Programmable RFSoC integrates up to 16×16 carrier-grade RF sampling ADCs and DACs tightly coupled to programmable logic and an ARM multi-processing subsystem. By eliminating discrete ADC and DAC components, systems can achieve up to 50-75 percent reduction in system power and footprint.
More than just RF data converters, the integrated block includes a power-efficient DSP subsystem for flexible configuration and RF signal conditioning. Specifically, the subsystem includes:
- Eight 4 GSPS or sixteen 2 GSPS 12-bit ADCs, with digital down-conversion (DUC);
- Eight to sixteen 6.4 GSPS 14-bit DACs, with digital up-conversion (DDC);
- Direct RF sampling for flexible analog design, greater accuracy, and lower power.
Direct RF sampling, or the ability to sample incoming signals directly without initial down conversion to an intermediate frequency (IF), provides RF designers greater flexibility. Digitizing the signal directly and then applying modern DSP techniques for signal conditioning yields better performance and programmability in the digital domain, particularly on an advanced 16nm FinFET process. To date, direct RF techniques have been incremental in adoption due to the economics and power inefficiency. Though direct RF sampling delivers flexibility in the digital domain, it uses more power as the sample rate rises, has a large footprint due to the use of many discrete components such as DACs and ADCs, and the BOM is large. Monolithically integrating this technology into the SoC itself increases this RF technique’s viability to the broader market. This integration of the RF data converter subsystem by the Zynq RFSoCs delivers lower power through integration, smaller footprint through integration, faster design cycle with less BOM complexity and flexibility in the digital domain.
According to Xilinx, direct RF sampling with Zynq UltraScale+ RFSoCs is easily acieved up to between 4- to 6-GHz depending on the application. Above 6-GHz downsampling is required but there are still the power and size reduction benefits that can be realised in the sub-6-GHz portion of the system.
Critical to the RF signal chain and all communications is forward error correction. This DSP technique corrects signal impairments in data transmission across various transmission mediums such as copper cable, optical fiber, or the air interface. Due to the high throughput requirements of next generation wireless and cable broadband, both the 5G access/backhaul and DOCSIS 3.1 standards require a more compute-intensive FEC coding scheme known as Low Density Parity Check (LDPC) codes in order to maximize spectral efficiency in RF transmission.
While LDPC implementations can range from soft IP in FPGAs to fixed and hardened cores in ASSPs or ASICs, the Zynq UltraScale+ RFSoC balances flexibility, throughput, and power efficiency with the first hardened and fully programmable LDPC encoding/decoding cores in a programmable device.
Capabilities include:
- Up to 42 Gb/s LDPC encode and 10 Gb/s decode system throughput;
- Turbo Decode for LTE backward compatibility with 4G LTE-Pro and LTE-Advanced;
- 80 percent less dynamic power than a soft IP implementation;
- Flexible, customizable LDPC codes for evolving standards and differentiation;
- Soft-decision decoding for greater reliability.
With compute-intensive matrix multiplication and continuous read and write to memory, hardening the SD-FEC can meet next generation standards for high throughput systems, such as 5G baseband.
From direct-RF conversion and signal conditioning, to acceleration and differentiation in FPGA logic, to correction of signal impairments, Zynq UltraScale+ integrates a comprehensive RF signal chain. Capabilities across the signal chain include:
- RF signal conditioning in the integrated data converters;
- Linearization, correction, differentiation, and acceleration with soft IP and custom FPGA logic;
- Baseband processing and acceleration, and error correction with integrated DSP and FEC cores;
- Multiple 100G Ethernet MAC cores;
- 33 Gb/s transceivers for evolving connectivity standards.
Tightly coupled to an ARM® processing subsystem, the RFSoC provides a unified platform for analog, digital, and embedded design, simplifying calibration and synchronization along the signal chain.
To summarize, devices in the family feature:
- Eight 4GSPS or sixteen 2GSPS 12-bit ADCs;
- Eight to sixteen 6.4GSPS 14-bit DACs;
- Integrated SD-FEC cores with LDPC and Turbo codecs for 5G and DOCSIS 3.1;
- ARM processing subsystem with Quad-Core Cortex™-A53 and Dual-Core Cortex™-R5s;
- 16nm UltraScale+ programmable logic with integrated Nx100G cores;
- Up to 930,000 logic cells and over 4,200 DSP slices.
Applications addressed by the Zynq RFSoC family include remote radio head for massive-MIMO, millimeter wave mobile backhaul, 5G baseband, fixed wireless access, remote-PHY nodes for cable, radar, test and measurement, SATCOM, military communications, airborne radio and other high performance RF applications.
Zynq UltraScale+ RFSoC devices now make viable the most bandwidth intensive systems for next generation wireless infrastructure. 5G imperatives—ranging from 5X bandwidth, 100X user data rates, and 1000X greater network capacity—would be unattainable without breakthroughs at the system level. The integration of discrete RF data converters and signal chain optimization in Zynq UltraScale+ RFSoCs allow remote radio head for massive-MIMO, wireless backhaul, and fixed wireless access to realize high channel density with 50-75 percent power and footprint reduction. Multiple integrated SD-FEC cores enable 10-20X system throughput versus a soft core implementation for 5G baseband within stringent power and thermal constraints.
Similarly, in next-generation cable broadband services, Zynq RFSoCs provide a combination of small form factor, power efficiency, and hardware flexibility to enable Remote-PHY systems. Distributed access architectures push DOCSIS 3.x PHY functionality from the centralized headend equipment to the Remote-PHY node located closer to consumers. By replacing inefficient analog optical transmission with ubiquitous Ethernet transport, network capacity, scale and performance improves. With RF integration and an LDPC FEC-enabled signal chain, RFSoCs ensure flexible R-PHY deployment for greater spectral efficiency prescribed by DOCSIS3.1.
Zynq RFSoCs also deliver the needed performance and adaptability for key government programs such as the Multi-function Phased Array Radar (MPAR) initiative to combine the functions of several national radar networks into a single system for aircraft and weather surveillance. Because these leading edge systems must operate in real time, the inherent integration of RF-Analog makes the Zynq UltraScale+ RFSoC an ideal solution. Zynq RFSoC devices are currently designed into the Rockwell Collins’ Common Module beamformer for the DARPA Arrays at Commercial Time Scales (ACT) program, which aims to shorten design cycles and in-field updates, while pushing past traditional barriers for delivering radar arrays.
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