Xilinx wraps FPGAs into programmer-friendly reconfigurable-computing environment
SDAccel combines what Xilinx presents as the industry’s first architecturally optimising compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries and development boards.
The architecturally optimising compiler is also said to deliver 3-times the performance and resource efficiency of other FPGA solutions, letting developers use a familiar workflow to optimise their applications and take advantage of FPGA platforms with no prior FPGA experience.
The integrated design environment (IDE) provides coding templates and software libraries, and enables compiling, debugging, and profiling against the full range of development targets including emulation on x86, performance validation using fast simulation, and native execution on FPGA processors.
It executes the application on data centre-ready FPGA platforms complete with automatic instrumentation insertion for all supported development targets.
SDAccel has also been architected to enable CPU/GPU developers to migrate their applications to FPGAs while maintaining and reusing their OpenCL, C, and C++ code in a familiar workflow. The SDAccel environment includes the programmer-ready IDE, C-based FPGA optimised libraries, as well as commercial off-the-shelf (COTS) platforms from partners such as Alpha Data, Convey or Pico Computing, ready for data centre use.
SDAccel libraries include OpenCL built-ins, DSP, Video, and linear algebra libraries for high performance, low power implementations. For domain specific acceleration, optimised OpenCV and BLAS OpenCL compatible libraries are available from Xilinx Alliance member Auviz Systems.
Claimed as unique to FPGA solutions, and like CPU/GPUs, SDAccel keeps the system functional during program transitions. It creates FPGA-based compute units that can load new accelerator kernels while an application is running. Throughout application execution, critical system interfaces and functions such as memory, Ethernet, PCIe and performance monitors are kept live. On-the-fly reconfigurable compute units allow FPGA accelerators to be shared across multiple applications. For example, operational systems can be programmed to switch between image search, video transcoding and image processing.
Xilinx; www.xilinx.com/sdaccel
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