Xilinx’ Zynq UltraScale+ RFSoC chips integrate the RF signal chain
Following a recent announcement of the technology, Xilinx has announced that it is now shipping its RFSoC family devices, that it presents as a means of saving power and space, by integrating many functions – particularly high-speed ADCs and DACs – alongside programmable logic and other ‘hard’ function blocks.
As part of the announcement, Xilinx has fleshed out the details of the configuration of the SoCs in the family, that shapes them for their intended markets of 5G Wireless, Cable Remote-PHY, and Radar.
Based on 16nm UltraScale+ MPSoC architecture, the all-programmable RFSoCs monolithically integrate RF data converters for up to 50-75% system power and footprint reduction, and soft-decision Forward Error Correction (SD-FEC) cores to meet 5G and DOCSIS 3.1 standards. An early access program for the Zynq UltraScale+ RFSoC family is now available.
Zynq RFSoCs combine RF data converters and SD-FEC cores with high performance 16nm UltraScale+ programmable logic and ARM® multi-processing system to create a comprehensive analogue-to-digital signal chain. While RF to digital signal conditioning and processing is typically segmented into stand-alone subsystems, the Zynq UltraScale+ RFSoC brings analogue, digital, and embedded software design onto a single monolithic device for system robustness. Devices in the family feature:
– Eight 4 GSPS or sixteen 2GSPS 12-bit ADCs
– Eight to sixteen 6.4GSPS 14-bit DACs
– Integrated SD-FEC cores with LDPC and Turbo codecs for 5G and DOCSIS 3.1
– ARM processing subsystem with Quad-Core Cortex-A53 and Dual-Core Cortex-R5s
– 16nm UltraScale+ programmable logic with integrated Nx100G cores
– Up to 930,000 logic cells and over 4,200 DSP slices
Alongside this list, Xilinx emphasises that these are monolithic devices; they do not use the company’s “2½-D” multi-chipo-plus-interposer technology.
Power savings come from a variety of sources, but in particular, a less integrated design will required high-bandwidth interfaces from data converter to FPGA – typically, JESD204B serial links. On-chip connectivity reduceds the power burden of transmitting that high-speed data.
Applications that Xilinx aims to address with the Zynq RFSoC family include remote radio head for massive-MIMO, millimeter wave mobile backhaul, 5G baseband, fixed wireless access, Remote-PHY nodes for cable, radar, test & measurement, SATCOM, and Milcom / Airborne Radio and other high performance RF applications.
In 5G wireless, the presence of multiple integrated SD-FEC cores enables a claimed 10-20X system throughput vs. a soft core implementation for 5G baseband within stringent power and thermal constraints. Massive-MIMO is assisted by the presence of multiple fas data converters on the same device. Error correction has been split between hard and soft functions; FEC is so processing-intensive that its core algorithms are supported in hard-diffused blocks – but leaving sufficient flexibility for users to optimise their signal flows with programmable logic. Turbo decode, conversely, is performed by “soft” logic, as IP blocks in the programmable logic.
In next-generation cable broadband services, Zynq RFSoCs provide a combination of small form factor, power efficiency, and hardware flexibility to enable Remote-PHY systems. Distributed access architectures push DOCSIS 3.x PHY functionality from the centralized headend equipment to the Remote-PHY node located closer to consumers. By replacing inefficient analogue optical transmission with Ethernet transport, network capacity, scale and performance improves. With RF integration and an LDPC FEC-enabled signal chain, RFSoCs provide flexible R-PHY deployment for greater spectral efficiency prescribed by DOCSIS3.1.
As with massive-MIMO, multiple data converters can meet the needs of many-channel, phased-array radars. Xilinx cites efforts such as Multi-function Phased Array Radar (MPAR) initiative to combine the functions of several radar networks into a single system for aircraft and weather surveillance. Because these systems must operate in real time, the inherent integration of RF-analogue makes the Zynq UltraScale+ RFSoC a suitable solution.
Tol support in the Vivado Design Suite – early access supporting Zynq UltraScale+ RFSoC devices – is now available.
Xilinx; www.xilinx.com/rfsoc
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