ZeroASIC launches simplified open source FPGA toolchain
ZeroASIC has launched a lightweight open source FPGA toolchain to automate circuit design using a simple Python script.
The Logik FPGA toolchain is powered by the ZeroASIC Silicon Compiler framework to easily generate bitstreams for FPGAs. This is achieved through a Python-driven, single execution step by sequencing the execution of multiple open source tools in an FPGA CAD tool chain.
In addition to Silicon Compiler, Logik builds on top of other well established open-source projects used in FPGA design flows, including the Yosys logic synthesis tool, VPR FPGA place and route tool, GHDL VHDL parser and Surelog SystemVerilog parser.
The Logik interface is driven by a short Python script from the user to aggregate design data and execute the flow. Logik executes the FPGA synthesis, placement, routing, and bitstream generation in sequence. Silicon Compiler’s metrics reporting features are used to report key results when the job is done.
The Logik flow is currently offered with built-in support for a single FPGA device called logik_demo. The logik_demo FPGA offers 6576 4-input LUT/flip-flop pairs, 16 multiply-add engines (MAEs), and 16 block RAMs as its logic resources.
For I/O interfaces, logik_demo offers 64 general-purpose I/O and three universal memory interfaces (UMI). In addition to using the logik_demo architecture to evaluate the RTL-to-bitstream flow, users may simulate generated bitstreams in the cloud with Zero ASIC’s digital twin platform.
Developers can extend Logik’s support to the FPGA architecture of their choice. The requirements for doing so consist of developing a VPR-compatible model of the FPGA, architecture metadata files to support bitstream generation, and a lightweight Python driver to integrate the FPGA into Logik.
Details on how to install and use the FPGA toolchain are on the Logik Github repository.
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
