Ziptronix to deliver lower-cost 3D memory with direct interconnect wafer bonding
Memory stacking is one of the most intriguing applications of 3D integrated circuit technology, as it has the potential to enable much higher memory density in a given footprint. But to date, process costs have been high, driven by the challenges of die thinning, handling of the thinned dies, and development of reliable interconnect processes.
Ziptronix DBI, which combines proprietary wafer-level low-temperature oxide bonding and interconnection, is showing substantial cost reductions in customer-driven development work focused on server and portable memory applications. That work is now moving into the prototype evaluation stage.
DBI has been proven in the backside imaging (BSI) sensor marketplace, another cost-sensitive sector, and can deliver cost savings of up to 80 percent compared to copper thermo-compression bonding. Because DBI creates extremely strong low-stress bonds, it allows wafers to be processed and thinned after bonding, greatly simplifying process requirements by eliminating the need to handle thinned wafers and/or dies. In addition, DBI is claimed to offer the highest available interconnect density and alignment accuracy. It is fully compatible with damascene interconnect processing, opening new avenues for foundry-based through-silicon via process flows. Ziptronix says that the uniform, high hybrid bond strength of the DBI process enables the highest vertical stacking density, and the thinnest overall height of finished 3D devices. It also supports a range of post-bonding test and repair strategies.
Visit Ziptronix at www.ziptronix.com
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