1.2 trillion transistors on a wafer-scale chip

August 20, 2019 // By Rich Pell
Trillion transistor chip is built for AI
AI compute acceleration startup Cerebras Systems (Los Altos, CA) has unveiled what it says is the largest chip ever built, comprising more than 1.2 trillion transistors.

Measuring 46,225 mm 2 and optimized for AI work, the Cerebras Wafer Scale Engine (WSE) is 56.7 times larger than the largest graphics processing unit, which measures 815 mm 2 and contains 1.2 trillion transistors. The WSE, says the company, also contains 3,000 times more high speed, on-chip memory, and has 10,000 times more memory bandwidth.

"Designed from the ground up for AI work, the Cerebras WSE contains fundamental innovations that advance the state-of-the-art by solving decades-old technical challenges that limited chip size - such as cross-reticle connectivity, yield, power delivery, and packaging," says Andrew Feldman, founder and CEO of Cerebras Systems. "Every architectural decision was made to optimize performance for AI work. The result is that the Cerebras WSE delivers, depending on workload, hundreds or thousands of times the performance of existing solutions at a tiny fraction of the power draw and space."

In AI, says the company, chip size is profoundly important, with bigger chips being able to process information more quickly, producing answers in less time. Reducing the time-to-insight, or "training time" - a major bottleneck to industry-wide progress - allows researchers to test more ideas, use more data, and solve new problems.

The chip's performance gains are accomplished by accelerating all the elements of neural network training. A neural network is a multistage computational feedback loop. The faster inputs move through the loop, the faster the loop learns or "trains." The way to move inputs through the loop faster is to accelerate the calculation and communication within the loop.

With 56.7 times more silicon area than the largest graphics processing unit, the WSE provides more cores to do calculations and more memory closer to the cores so the cores can operate efficiently. Because this vast array of cores and memory are on a single chip, says the company, all communication is kept on-silicon providing breakthrough bandwidth so groups of cores can collaborate with maximum efficiency, and

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.