TCAD simulations of the forksheet device with reduced n-to-p spacing show a 10 percent performance increase compared to nanosheet devices and a 20 percent cell area reduction compared to gate-all-around nanosheet devices. When combined with scaling boosters, the new device architecture will bring logic standard cell height down to 4.3 tracks, which combined with cell template optimization can result in more than 20 percent area reduction, the researchers say.
The forksheet device has recently been proposed by imec as a natural extension of vertically stacked lateral gate-all-around nanosheet devices. Contrary to the gate-all-around nanosheet device, in the forksheet, the nanosheets are now controlled by a tri-gate forked structure, realized by introducing a dielectric wall in between the P- and NMOS devices before gate patterning. This wall physically isolates the p-gate trench from the n-gate trench, allowing a much tighter n-to-p
spacing – a challenge that could not be answered with FinFET or nanosheet structures.