Intel and Micron chose not to reveal the materials they are using or the switching mechanism at play in their 3D XPoint non-volatile memory launched earlier this week. But there is some circumstantial evidence for it being phase-change memory technology implemented in a 2Xnm or 1Xnm manufacturing process. The scaling, novel mixes of chalcogenide glass and other developments may have provided the claimed performance improvements.
The 2Xnm feature size can be derived from calculations based on a typical die size, the assumption of a 4F2 memory cell, and the given information of two planes of 64 billion memory cells in the 128Gbit 3D Xpoint memory. A die area of 1 square centimeter yields a feature size of 19nm or less. A larger die would push the upper limit up to the 27nm region.
The secrecy has given rise to much speculation about the underlying 3D XPoint technology. Rob Crooke, general manager of the non-volatile memory group at Intel, and Mark Durcan, CEO of Micron, described it as a fundamental breakthrough. They also said it was "bulk switching" suggesting a non-filamentary behavior.
Intel did say that 3D XPoint should not be described as a ReRAM but the nomenclature definition of what is or is not a resistive RAM is not formal. Intel also said the 3D XPoint memory cell operates via changes in resistance of the bulk material, which makes it a resistive RAM by the broadest definition, but includes the possibility of it being a phase-change memory.
Also I am not sure I would describe phase-change memory as a bulk phenomenon as it results from a thermal pulse that proceeds from an electric current through the material. But it could be argued that in a sufficiently small cross-point a significant amount of the active material undergoes the phase change.
And then there are similarities between 3D XPoint and physical layout diagrams of previous presentations on PCMS – a stacked arrangement