The XCZU19EG FPGA has 1968 DSP Slices and 1143K logic cells, and includes a quad-core ARM Cortex-A53 processor, dual-core ARM Cortex-R5 and ARM Mali-400 MP2 GPU. The Cortex-A53 Dual GbE is accessible directly from 1000-BaseBX connection to P1. The FPGA interfaces directly to the VPX P1-P2 connectors via LVDS, GPIO and high-speed SERDES, and to FMC+ DP0-15 and all FMC LA/HA/HB pairs.
Each FMC+ site has 16 GTP SERDES routed from the FPGA and each site is supported by an Interlaken hardcore processor. The boards provide 8GB of DDR4 via a 64-bit wide memory channel, allowing for large buffer sizes to be stored during processing as well as for queuing data to a host processor. The module also includes 64 GB of Flash, 128 MB of Boot Flash and a SD Card option. An on-board microcontroller implements Tier 2 system management per VITA 46.11, supporting advanced features such as sensor management and event logging, making the unit suitable for deployment in large and complex systems.
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