Mirabilis Design in the US has developed a simulator that combines fast processor models with hardware libraries for exploration of an entire design in software before hardware or software development starts.
The VisualSim VPS tool combines VisualSim semiconductor, embedded and network libraries with the software execution Gem5 Instruction Set with templates for automotive, medical, IoT, industrial and space applications, particularly using machine learning and AI.
Adding the Gem5 fast fuctional processor models means VisualSim VPS supports 32bit and 64-bit architectures, multi-core, and out-of-order processors. Instruction sets available are ARMv7, ARM v8, ARM SVE, RISC-V, x86, Power and CUDA GPU. All Instruction Sets come pre-loaded with Linux and a graphical debugger.
“Our customers can now map the software task graph onto a hardware platform, get the scheduled optimized and then immediately start the software development,” said Deepak Shankar, Founder of Mirabilis Design. “This new approach saves months from the current methodology for software development. Based on our early customer experience, we have seen projects save almost six months and reduce costs by 15 percent,”
VisualSim VPS has been tested with Electronic Control Units, Infotainment systems, AI processors and hybrid prototyping of Radar systems. This helps to improve the quality of architecture exploration, enables accurate performance testing, integrates research and product development, simulate the entire system or semiconductor prior to development, and shift software development to systems engineering.
This also allows systems engineers to generate task graphs of the software so that hardware engineers can map it to architecture models to experiment with integrated vs. distributed, multi-core vs. multi-processor, multi-thread vs. single-thread, and ARM vs. RISC-V. Software developers can then replace parts of the task graph with the software running on the Instruction Set while hardware engineers can replace with physical prototypes, offering a flow from concept to debugging.
This creates a collaborative platform for OEM, suppliers, and semiconductor vendors as the first stage of a digital twin.