Aldec has added an automatic UVM Generator function to create testbenches in SystemVerilog for FPGA and system-on-chip designs.
The generator aims to boost the productivity of Riviera-PRO users taking advantage of the benefits of the Universal Verification Methodology, which contains guidance on the creation and reuse of verification testbenches.
The tool automatically creates the UVM testbench in SystemVerilog for any given design under test (DUT) written in VHDL or Verilog. It also creates a framework of the UVM code that contains comments indicating places that must be manually populated with design-specific code. Along with SystemVerilog source files, the UVM Generator automatically creates the TCL macros for controlling the simulation process. The user can choose a DUT from a library or start a new design from scratch.
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Riviera-PRO combines a simulation engine and debugging capabilities at different levels of abstraction with support for the latest Language and Verification Library Standards. The UVM-generated code can also be displayed in Riviera-PRO’s UVM Graph Window to provide visualization of the hierarchical UVM components, properties, connections, and dataflow to help wth debugging.
“While not the only verification methodology available, UVM is certainly one of the most popular – particularly since its standardization by the IEEE in 2017,” said Sunil Sahoo, Aldec’s SW Product Manager.
Aldec has also updated the Open-Source VHDL Verification Methodology (OSVVM) library to version 2021.06 within Riviera-PRO. In addition, the tool’s Universal VHDL Verification Methodology (UVVM) utility (uvvm_util) and VHDL Verification Component Framework (uvvm_vvc_framework) libraries have been updated to version v2021.05.26.
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