Ampere debuts 80-core ARM server processor

March 03, 2020 //By Peter Clarke
Ampere debuts 80-core ARM server processor
Ampere Computing LLC has announced a 64-bit ARM-based processor for servers comprising 80 cores and targeting 7nm manufacturing process technology.

Altra is a follow-up to the 32-core Skylark processor, otherwise known as eMAG, which has been manufactured in TSMC's 16nm FinFET process. Even as that product came to market in 2018 the company was advising of a 7nm processor to follow (see Startup Ampere prices ARM server chips ).

 

Altra is an 80-core processor based on Neoverse N1 license, designed for predictable high performance, security isolation, scalability and leading power efficiency. It comes in single socket and dual socket versions, which are sampling to customers.

 

The device is scalable up to 80 cores per chip with a power consumption footprint of up to 210W. The cores are specificed up to 3.0GHz clock frequency. The core is a four-instruction wide superscalar out-of-order processor based on the ARMv8.2 instruction set architecture. Each core is single-threaded to provide reduced performance variability and increased security against system-level side-channel attacks.

 

There are 64kbyte level-one instruction and data caches per core and 1Mbyte level 2 data caches per core. There is also a processor-wide 32Mbyte system-level cache.

 

There are 8 72bit-wide DDR4 interfaces per chip and 128 lanes of PCIe Gen4 for highest IO bandwidth.

 

Altra is Ampere's cloud-focused product, and first in a new class of CPUs rolling out on an annual basis from Ampere’s roadmap. The increased performance and power efficiency will make Altra suitable for many workloads including data analytics, artificial intelligence, database, storage, telco stacks, edge computing, web hosting and cloud native applications.

 

Jeff Wittich, senior vice president of products at Ampere, said that for some intensive training loads arrays of GPUs or some more specialized tensor processors or neural network accelerators could possibly provide superior power efficiency. "Training on TPU, IPU or GPU can make sense, but inference we can do. In other circumstances we will be the host node for an accelerator," he told eeNews Europe .

 

"Our team’s attention is on solving


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