Analysis tool reads through chips’ architectures: Page 2 of 4

April 17, 2019 //By Julien Happich
Analysis tool reads through chips’ architectures
Back in 2016, chip security analysis startup Texplained was making its first investments in laboratory equipment, analyzing various chips’ internals and commercializing its reports as a catalogue of heavily scrutinized reverse-engineering IPs, identifying security weaknesses.

Automated layers alignment, via upon via (source: Texplained).

“What has been missing so far for governments wanting to check on the vulnerability of a chip or to investigate the presence of a backdoor is an efficient and reliable tool to read through the chips’ internals”, Ginet said, adding that Texplained has several patents pending on a novel method to precisely align all the layers and extract correct circuit information.

“Most labs use different scripts or try to integrate in-house tools with external solutions but the overall extraction reliability if fairly low. In contrast, our tool is highly reliable, allowing our customers to align different chip layers and correlate them perfectly using only high-resolution images, both at the via and trace level, which enables a consistent image stitching for the accurate mapping of a chip, both in 2D at a given layer and in 3D from one layer to the next”.

The tool will only be licensed to select organisations, as if it fell into the wrong hands, it could definitely be misused, including for IP theft.

“Governmental customers would want to check for possible backdoors, comparing a real chip architecture at the end of production line, to its golden standard, and making sure that no IP has been added or modified at foundry-level, eventually figuring out what functionality would those extra transistors bring” explained Ginet.

Picture: 
IC reverse-engineering

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