Analysis tool reads through chips’ architectures: Page 4 of 4

April 17, 2019 //By Julien Happich
Analysis tool reads through chips’ architectures
Back in 2016, chip security analysis startup Texplained was making its first investments in laboratory equipment, analyzing various chips’ internals and commercializing its reports as a catalogue of heavily scrutinized reverse-engineering IPs, identifying security weaknesses.

“Finding equivalences at the functional level was not our initial target, but this will be part of future functionalities of our software” Ginet said, adding that currently the tool is using machine learning to automatically extract in parallel the netlist from the hundreds of millions of transistors it sees.


A shot showing the feature and via detection as well
as all the design instances detection (source: Texplained).

“We developed the scripts to analyse the netlist as a primary analysis, then we can trace the signals and filter the design blocks by field of interest, for example only looking for clock trees, voltage rails etc… Once the extraction is in place, we’ll need to push our machine learning algorithms further for other features or functionality detection”.

With this announcement, Texplained still wants to offer its consultancy services and offer new chip reports on its website, but for that it will need to expand its R&D capacity.

“We want to take on more projects and analyse more chips, but currently, we have a bottleneck at the lab and more customer demand than what we can address. We are about to acquire new equipment to double our capacity”, concluded the CEO.

 

Texplained – www.texplained.com

Related articles:

Stepping up security in chip design: Texplained

French startup hacks secure chips for the common good

Picture: 
IC reverse-engineering

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