We also took the opportunity to ask Yeric about the industry's silicon manufacturing roadmap and ARM's view of the likely path beyond 3nm where there is considerable uncertainty.
Yeric: "We're going to need new ways of doing things to get to 2nm and 1nm. We do have a physical IP business and we need to pay attention because they may need to make changes at some point."
Yeric said that right now the emerging favourite is to go to multiple channels in a FinFET in the so called "nanosheet" approach and then to stack p- and n-type FinFETs one above the other in the so-called complementary FET or CFET configuration (see IMEC presents 'n-over-p' complementary FET proposal). And after that is possible to think of applying 3D stacking learning from 3D-NAND to logic. "At a cost level that is an alternative but we don't know about power and performance. But we are already getting used to not seeing those power-performance benefits," said Yeric.
A lack of performance uplift and power saving from miniaturization means that value has to be created in design and if anything that plays to ARM's strength, he said. "With ideas like memory near compute, compute in memory and so on, there is plenty of opportunity a the system level," he said.
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