UK chip design house Sondrel has launched a family of reference designs that could reduce design costs, risk and time by up to 30 percent compared to starting from scratch. The company has drawn on its experience of hundreds of ASIC designs to create a set of key reference designs that each provide a faster design time for high growth markets.
The first ASIC reference design is aimed at fixed and mobile (battery powered) applications, such as Smart Home, Smart Metering, Sensor Fusion and other occasions where a compact chip can add local end-point data processing for data collection and analysis along with inference processing. This SFA200 can be scaled with multiple units if required.
Sondrel will be releasing more than five IP platforms in this family through the year that target advanced nodes to provide cost effective devices. Two will be targeted at ADAS while the other three have scalable amounts of processing power that address the needs of different application areas.
“In a given application area, there is always considerable duplication in the design of each ASIC as there is a lot of communality in the interconnections and supporting IP that forms the architecture of the device,” said Graham Curren, Sondrel’s CEO.
“Rather than start from scratch with each new design, we have created reference designs that distils our experience of designing the architecture for such chips to create reusable IP platforms. Onto this, we add the customer’s IP with some customisation to create a bespoke solution for that customer,” he said. “This reduces the overall design costs and risk as our IP platform is tested and ready to use which also means that the time to market is reduced as well. We estimate that this approach, which we are calling Architecting the future, will provide time and cost savings of up to 30 percent for customers.”