The Spice models for a range of Bizen devices have been completely rewritten by the team at SFN, which includes researchers from the University of Nottingham. There is also a complete physical design kit (PDK) for the Cadence design flow, says Summerland.
The current approach allows for analogue computing, where currents can be combined and grow over time, and this is one of the first products for early in 2020. “The Programmable Junction Transistor (PFT) means we can integrate high voltage and logic on the same die in 8 layers without using a SOI substrate,” he said. “It has been difficult to get the combination of power and logic, and if it is just logic its less layers.”
“We will release the PJT in Q1 and Q2 and that’s where we expect to get fab uptake on the process,” he said. “We believe the process will scale beyond 1um but that’s not proven yet. We are actively looking at a scaling project and our simulation says it will.”
This could open up logic production at older fabs, they say. “If it can be adopted by the industry, an important prize given the reduction in die area at a given technology node comparing a Bizen and CMOS logic implementation would be the ability to wind back the Moores’ Law clock by 10 years or more and bring many wafer fabs back into mainstream manufacture," said James. “There is still a way to go before Bizen becomes a commercial reality and we are still learning, however Semefab and SFN are working flat out to make it the huge success it may soon become.”