The book examines the breadth of nanoelectronics in detail but its most significant finding is towards the end of the book and is at the global scale: that the proliferation of nanoelectronics is set to produce blackout failures of the Internet by 2020 due to an electrical power singularity.
Like the previous book it has been written under Hoefflinger's guiding editorship but with contributions from numerous authors from across the semiconductor and electronics fields to cover a wide range of topics.
The previous book was written to explore the imminent end of the electronics miniaturization roadmap at somewhere between 20 and 10nm and resulted in a discussion of the need to scale energy consumption rather than, or as well as, physical dimensions. Although the end of scaling is debatable it is clear that the economics that drove Moore's Law have changed and that energy is a now a key factor in design consideration.
CHIPS 2020 Volume 2 has sought to present the latest developments in the most critical and promising areas relevant to energy efficient electronics. The need to develop in these areas is illustrated by Hofflinger's own discussion of the potential of the Internet of Things to prompt a global energy-resource crisis.
As in the previous book some of the chapters explore more radical developments currently in academic research, perhaps because the traditional evolutionary development of such standard approaches as CMOS logic appear to lack the ability to produce energy savings compatible with sustainability.
Notable contributors from the commercial sector include: Udo-Martin Gomez of Bosch Sensortec GmbH, Peter Hans Roth and Cedric Lichtenau of IBM; Jiri Marek of Robert Bosch GmbH and Zvi Or-Bach, founder of Monolithic 3D Inc.
Hoefflinger has contributed the opening chapter on the future of eight specific chip technologies, as he did in the 2012 book. His conclusion includes the observation that: "The inertia in exploiting the hundreds of billions of dollars invested in standard fully complementary CMOS libraries has caused little progress in the energy-efficiency of processors, other than attempts to improve the energy-efficiency by turning down the supply voltage, with dramatic losses in speed…."
Hoefflinger references a throughput figure of merit (FoM) based on operations per second divided by energy consumed per operation and asserts that differential transmission-gate logic (DTL) beats standard cell logic by an order of magnitude, both in energy efficiency and in throughput FoM. DTL is a development reported by two researchers from KU Leuven, Belgium – Nele Reynders and Wim Dahaene – in a 2014 ISSCC paper, A 210mV 5MHz variation-resilient near-threshold JPEG encoder in 40nm CMOS.
Next: Breadth of coverage