Broadcom is sampling its first 5nm ASIC device for data centre and cloud infrastructure.
The chip is built on TSMC’s N5 process and measures 625 mm 2 with PCIe Gen5 protocol, 112-Gbps SerDes, HBM2e memory operating at 3.6 Gbps, and 3.6-Tbps Die2Die PHY IP using TSMC's CoWoS interposer technology. CoWoS (Chip-on-Wafer-on-Substrate) allows multiple die side-by-side on a silicon interposer interconnected with micro-bumps.
The company has a number of ASICs in development on the N5 process targeting artificial intelligence (AI), high performance computing (HPC) and 5G wireless infrastructure applications with twice the performance for training and inference applications.
The N5 process supports high speed multi-protocol 112-Gbps, 64-Gbps and 32-Gbps SerDes cores as well as HBM2e and HBM3 high speed memory interfaces to reduce latenmcy in data centre designs. The high bandwidth Die2Die PHY allows for multiple die in a package and silicon disaggregation, better known as chiplets. The process also supports multi-chip-modules and 2.5D stacking.
“Broadcom’s pioneering ASIC leverages both N5, the industry’s most advanced silicon technology, and our high-performance CoWoS integration solution to address the demanding requirements of next-generation cloud and data center applications,” said Dr. Kevin Zhang, senior vice president of business development at TSMC. “We’re excited to see the new applications Broadcom’s ASIC platform will enable, and look forward to continued partnership to empower end customers and their innovations.”
“This first-to-market 5nm ASIC extends Broadcom’s embedded SoC leadership and paves the way for new innovations across AI, HPC, 5G and hyperscale infrastructure applications,” said Frank Ostojic, senior vice president and general manager of the ASIC Product Division at Broadcom. “Our innovative IP, proven design methodology and partnership with TSMC continue to provide leadership solutions with power, performance and time to market advantage for our customers.”
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