Building flexible microprocessors from 2D-material transistors

April 26, 2017 //By Julien Happich
Building flexible microprocessors from 2D-material transistors
Using transistors made from layers of molybdenum disulphide (MoS2), a 2D material, researchers from the Graphene Flagship have devised an ultra-thin processor chip integrating 115 transistors and capable of 1-bit logic operations, all in a 0.6mm2 area.

The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. What's more, the design is readily scalable to multi-bit data, the researchers claim, hoping these ultra-thin devices, flexible

Their paper "A microprocessor based on a two-dimensional semiconductor" published in Nature Communications explains that although the microprocessor was fabricated in gate-first technology on a silicon wafer with 280-nm-thick silicon dioxide, the silicon wafer was merely used as a carrier medium and could easily be replaced by glass or any other material, including flexible substrates.

"We fabricated 18 devices per wafer, with FET channels made from chemical vapour deposition (CVD) grown large-area bilayer MoS2 films. Two Ti/Au metal layers were used to interconnect the transistors and Al2O3 was used as gate oxide", the researchers write in their paper. The MoS2 FET devices exhibited a field-effect mobility of around 3cm2 V−1 s−1, a threshold voltage VT of about 0.65V, an on/off ratio of about 108, and uniform behaviour over a 50mm2 area over the wafer.

Schematic drawing of an inverter circuit (top) and an individual MoS2 transistor (bottom) in gate-first technology.

Minimum feature size was kept to 2μm to make the design immune to sample in-homogeneities (such as small holes, cracks and contaminations in the MoS2 film) and also allows for fast visual inspection of the lithographic structures with an optical microscope. The circuit is based on the NMOS logic family, where both pull-up (load) and pull-down networks were realized using n-type enhancement-mode FETs with Width/Length ratios of 45/2 (μm/μm) and 7/5, respectively.

Transistor count was minimized for demonstration purposes, hence the single-bit data handling capability of the proof-of-concept 2D microprocessor. "We stress that this is not a fundamental limitation and the device is readily scalable to N-bit data, broadly speaking by connecting N of our devices in parallel", the researchers wrote.

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.