CacheQ Platform Revs Up Processor, FPGA Performance

September 24, 2019 //By William G. Wong
With the CacheQ Ultravisor, developers can deploy distributed computation to processors, GPGPUs, and FPGAs.

Distributed processing offers performance advantages, but programming it in a scalable fashion can be a challenge. Enterprise FPGA platforms like Xilinx’s Alveo and Intel’s PAC are popular because they can support parallel processing in programmable hardware. Unfortunately programming FPGAs isn’t an easy task either. Partitioning systems across a number of chips is even more difficult.

CacheQ has designed a heterogeneous distributed acceleration system that can target a range of platforms from arrays of processors to FPGAs. The company’s QCC Acceleration Platform is a development environment that handles these heterogenous computing resources. It’s designed to provide orders of magnitude of performance improvement while significantly reducing development time.

CacheQ targets a variety of platforms from GPGPUs to FPGAs.

“Demand for hardware acceleration beyond x86 is tremendous,” says Clay Johnson, chief executive officer and co-founder of CacheQ Systems. “Our goal is to simplify high-performance data center and edge-computing application development. The QCC Acceleration Platform meets that goal and will enable new solutions across a variety of applications, including life sciences, financial trading, government, oil and gas exploration, and industrial IoT.”

The platform is based on the CacheQ virtual machine (CQVM). Applications are compiled using an LLVM-based compiler that generates the CacheQ target language (CTL). This approach is typical for LLVM-based compilers, including popular C/C++ versions. In turn, it can be used to target a particular platform like an FPGA. A system can also be run through the virtual-machine optimizer and partitioner.

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