The Palladium Z2 Enterprise Emulation and Protium X2 Enterprise verification systems have been updated to address chip designs up to 19 billion gates. Both have a capacity of 1.2billion gates per rack and 16 racks can be connected together.
The Palladium Z2 has twice the capacity of the previous Z1 system from using both optical and copper interconnect covering all 4 edges of the board. However the key is a proprietary emulation processor architecture that provides fast predictable compile and at speed debug, says Cadence This ‘very fast logic evaluation processor’ uses Cadence’s own ISA and is built on a 16nm process.
The Protium X2 physical verification system can implement pre-silicon RTL to run software before a chip is built. This uses 60 FPGAs (up from 48 in the X1) per board using the logic fabric of the Xilinx U19P Ultrascale FPGAs. The 1.6x increase in the fabric in these devices doubles the number of FPGAs on the board, with 10 boards per rack, up from 8 in the X1 racks.
Both systems uses modular compilation technology capable of compiling 10 billion gates in under 10 hours on the Palladium Z2 system and in under 24 hours on the Protium X2 system and can run 60 concurrent jobs per rack including the peripherals and memory models.
40 percent of Cadence customers use both the Palladium and Protium systems for emulation of designs and early verification of software. Cadence says it supplies 12 of the top 15 semiconductor companies, including 4 out of the top 5 mobile phone application processor developers. Market researchers put Apple, Samsung, Qualcomm and Mediatek as the top four, with HiSilicon, the silicon subsidiary of Huawei, at number five, but subject to restrictions on the sale of US technology as part of the ongoing US-China trade war.
The Palladium Z2 and Protium X2 have an integrated design flow, unified debug, common virtual and