Cadence joins forces with TSMC and Microsoft to shrink IC signoff

June 16, 2020 //By Julien Happich
IC signoff
EDA vendor Cadence Design Systems announced the results of a three-way collaboration with TSMC and Microsoft focused on utilizing cloud infrastructure to reduce semiconductor design signoff schedules.

Through this collaboration, common customers will have an accelerated path to complete timing signoff by adopting the Cadence Tempus Timing Signoff Solution and the Quantus Extraction Solution using TSMC technologies on the Microsoft Azure Cloud with the Cadence CloudBurst Platform. By moving to the cloud, users from all vertical markets can achieve a significant productivity improvement without the constraints of on-premise hardware.

Both the Cadence Tempus Timing Signoff Solution and Quantus Extraction Solution feature massively parallel architectures that are optimal for use in the cloud. Utilizing unique distributed signoff technologies, the Tempus Timing Signoff Solution is production-proven in the cloud on large-scale TSMC advanced-node tapeouts.
The Cadence Tempus Timing Signoff Solution and Quantus Extraction Solution are part of the broader full flow digital suite, which provides customers with a fast path to design closure and better predictability. The CloudBurst Platform provides fast and easy access to Cadence tools and is part of the broader Cadence Cloud Portfolio.
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