Cadence moves verification IP up to the chip level

October 14, 2020 //By Nick Flaherty
Cadence moves verification IP up to the chip level
System-Level Verification IP (System VIP) is a suite of tools and libraries from Cadence Design Systems for automating full system-on-chip (SoC) design testing

Cadence Design Systems has launched a new tool offering ten times the efficiency in system-level testbench assembly, execution and analysis for hyperscale, automotive, mobile and consumer chips

The System-Level Verification IP (System VIP) is a suite of tools and libraries for automating system-on-chip (SoC) testbench assembly, bus and CPU traffic generation, cache-coherency validation and system performance bottleneck analysis. This allows designers to create complex hyperscale, automotive, mobile and consumer chips can improve chip-level verification efficiency by a factor of ten.

“Our system VIP solution takes IP level test to the chip level – this automates the generation of SoC test benches with complex,” said Paul Cunningham, general manager of the system verification group. “It includes CPU and bus traffic geenation, simulation, emulation, verification and even post silicon bring up.”

The tests are portable across Cadence simulation, emulation and prototyping engines and can also be extended to post-silicon bring-up. The tools include the System Testbench Generator that automatically generate SoC testbenches with complex memory, cache, interface and bus configurations as well as System Traffic Libraries that provide pre-defined tests that can be plugged into a System VIP testbench, including coherency, performance, PCI Express® (PCIe®) and NVMe subsystems

The System Performance Analyzer enables analysis reporting and visualization for memory subsystems, interconnects and peripherals while the System Verification Scoreboard provides comprehensive data and cache-coherency checks across coherent interconnects, memories and peripherals.

“Renesas has used Cadence VIP for many years and values Cadence’s leadership in advanced SoC verification technologies,” said Tetsuya Asano, director, Design Methodology Department, Shared R&D EDA Division at Renesas. “By adding the new System VIP to our existing verification environment based on the Cadence Xcelium and Palladium platforms, and improving stimulus re-use and automation, we’ve further accelerated the SoC verification process with 10X more efficiency, enabling us to deliver innovative, high-quality products to our customers faster.”

“Through our collaboration with Cadence, we’ve reduced some of the complex SoC verification challenges, especially around


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