Cadence streamlines DSP IP for vision, AI applications : Page 2 of 2

May 15, 2019 //By Christoph Hammerschmidt
Cadence streamlines DSP IP for vision, AI applications
AI algorithms such as Deep Learning and Machine Learning are being used in more and more applications - and the demand for computing power of the processors involved is increasing massively, while at the same time the chips must consume less and less power. The EDA software and IP provider Cadence Design Systems now wants to reconcile these conflicting requirements with a new high-end version of its Tensilica signal processor. Cadence's main focus is on image processing applications in vehicles and robotics.

The increasing demand for image sensors in edge applications has led to corresponding growth in the embedded vision market. Current image applications require a mixture of image processing and AI, whereby the corresponding edge SoCs must a highly flexible and very efficient image processing and AI solutions and at the same time consume very little power.

Twice the AI and floating point performance over its predecessor
at the same size: Tensilica Vision Q7 DSP (C) Cadence

In addition, edge applications with an integrated camera require a Vision DSP to be able to perform pre- or post-processing prior to an AI task. For SLAM processing, the corresponding edge SoC also requires an offload engine to increase performance, reduce latency, and ensure lower power consumption for battery-powered devices. Because SLAM operations use both fixed and floating point arithmetic to achieve the necessary accuracy, a vision DSP used for SLAM operations must provide high processing power for both data types.

With its low power consumption, its architectural and instruction set extension, the Vision Q7 DSP is designed to meet the needs of sophisticated edge vision and AI processing tasks. Cadence promises that the new DSP offers twice as much performance in AI and floating point computing tasks as its predecessor – at the same real-estate consumption on the chip. The enhanced instruction set now offers 8-, 16- and 32-bit data types; the VLIW SIMD architecture processes 1.7-times more instructions than the Vision Q6. For even higher AI throughput, the Q7 can be connected to the Tensilica DNA 100 processor.

Developed according to the requirements of key customers using complex vision and AI algorithms, the Vision Q7 DSP is expanding Cadence’s automotive portfolio in the first place. It supports AI applications developed with popular frameworks such as Caffe, TensorFlow and TensorFlowLite as well as the Tensilica Xtensa Neural Network Compiler (XNNC), which converts neural networks into executable and optimized code. The software environment also provides support for more than 1,700 OpenCV-based vision libraries, enabling rapid high-level migration of existing vision applications. Development tools and libraries have also been developed for SoC vendors to achieve ISO 26262 ASIL D (Automotive Safety Integrity Level D) certification.

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