Cadence Design Systems and United Microelectronics Corporation (UMC), a global semiconductor foundry have optimized and certified Cadence’s digital design flow for the UMC 22ULP/ULL process technologies. The move enables chip designers to speed consumer, 5G and automotive application designs. The flow incorporates implementation and signoff technology for ultra-low power designs.
The Cadence digital full flow that has been optimized for use on UMC’s 22ULP/ULL process technologies includes the Innovus Implementation System, Genus Synthesis Solution, Liberate Characterization, Quantus Extraction Solution, Tempus Timing Signoff Solution, Litho Physical Analyzer and Physical Verification System.
The combination of the Cadence flow and the UMC process enables a number of important features and functions, according to Cadence. Among other things, this includes significantly improved design implementation and optimisation engines. These are fully integrated from the RTL to the GDSII level, making it easier for chip designers to achieve ambitious power, performance and area (PPA) targets. It also helps shorten time-to-market.
Cadence thus offers what it claims is the only digital flow with fully integrated place-and-route, timing signoff, physical verification and IR drop/power signoff capabilities that enable design completion on the lowest number of iterations. This makes it easier to bring advanced node products to market in a comparatively short time.
To this end, UMC replaced its established library characterisation tool with Cadence Liberate Characterisation, which forms the basis for the broader digital full flow and is a key component enabling advanced timing and power analysis, optimisation and signoff goals.