C/C++ compiler and debugger toolchain supports RISC-V cores

May 22, 2019 //By Julien Happich
IAR Systems now supports RISC-V cores with its C/C++ compiler and debugger toolchain IAR Embedded Workbench.

According to the company’s own tests, the first version of the IAR C/C++ Compiler for RISC-V is proven to deliver major improvements in code density, generating code that is considerably smaller compared to code generated by other available tools. To ensure code quality, the toolchain includes C-STAT for integrated static code analysis. C-STAT can help prove compliance with specific standards like MISRA C:2004, MISRA C++:2008 and MISRA C:2012, as well as detect defects, bugs, and security vulnerabilities as defined by the Common Weakness Enumeration (CWE) and a subset of CERT C/C++. The C-SPY Debugger included with IAR Embedded Workbench gives full control of the application in real time, and its simulator provides full debugging capabilities even without access to the hardware. For in-circuit debugging, IAR Systems provides the probe I-jet, delivering a high-speed debugging platform with full code control.
RISC-V is a free and open instruction set architecture (ISA) based on established Reduced Instruction Set Computing (RISC) principles. In 2018, IAR Systems joined the non-profit RISC-V Foundation, which drives the adoption and implementation of the RISC-V ISA, and committed to bring its leading development tools to the growing RISC-V community.
The first version of IAR Embedded Workbench for RISC-V provides support for RV32 32-bit RISC-V cores and extensions. Future releases will include 64-bit support and support for the smaller RV32E base instruction set, as well as functional safety certification and security solutions.
IAR Systems - www.iar.com

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.