CMOS device fabrication at 500°C for 3D monolithic integration

June 23, 2020 //By Julien Happich
CMOS device
In an FDSOI CMOS processing breakthrough, CEA-Leti scientists have pushed fabrication thermal-process boundaries down to 500°C for CMOS integration, while showing strong performance gains especially in P-type metal-oxide-semiconductor (PMOS) logic devices.

The 500°C threshold is important because in 3D monolithic technologies (also called 3D sequential), fabricating the upper-level transistors at higher temperatures than that can damage the metal interconnects and the silicide of the bottom-level transistors. Using CEA-Leti’s CoolCube low-temperature process for top-level devices prevents deterioration of bottom-level transistors.

“Integration of CMOS devices is now possible at 500°C on top,” said CEA-Leti scientist Claire Fenouillet-Beranger. “This proof of concept gives more and more credibility to this sequential integration for applications requiring high density.”

In a paper titled “First demonstration of low temperature (≤500°C) CMOS devices featuring functional RO and SRAM bitcells toward 3D VLSI integration” which was presented virtually during the 2020 Symposia on VLSI Technology & Circuits, June 14-19, co-author Fenouillet-Beranger explains: “3D sequential integration becomes more and more attractive for More Moore and More than Moore applications. One of the main advantages of this 3D technology vs. a die-to-die one, for instance, is the major gain of density brought by the nanometer-scale lithographic alignment between the two levels. However, one of the most important challenges is to implement at low temperature high performance CMOS devices for the upper level, after fabrication of the bottom level devices”.


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