Microchip has developed a 1/6Tbit/s Ethernet PHY for the next generation of connections in data centres and 5G base stations.
The PM6200 META-DX2L supports the 112Gbit/s PAM4 Serializer/Deserializer (SerDes) protocol for 800G Ethernet. The PHY is packaged in a 23 x 30mm which enables the space savings necessary to deliver the line card port densities demanded by hyperscalers and system developers. It reduces the power per port by 35 percent compared to its 56G PAM4 predecessor, META-DX1.
“The industry is transitioning to a 112G PAM4 ecosystem for high-density switching, packet processing, and optics,” said Bob Wheeler, principal analyst for networking at The Linley Group. “Microchip’s META-DX2L is optimized to address these demands by bridging line cards to switch fabrics and multi-rate optics for 100 GbE, 400 GbE and 800 GbE connectivity”.
Highly configurable crosspoint and gearbox features make full use of a switch device’s I/O bandwidth to enable the flexible connections necessary for multi-rate cards that support a wide range of pluggable optics. An integrated 2:1 hitless mux enables high availability/protection architectures.
The PHY’s low-power PAM4 SerDes enables it to support the next-generation infrastructure interface rate for Ethernet, OTN, and Fibre Channel data rates in cloud data centers, AI/ML compute clusters, 5G, and telecom service provider infrastructure, whether over long-reach direct attach copper (DAC) cables, backplanes, or connections to pluggable optics. The chip supports 32 long-reach (LR) capable 112G PAM4 SerDes lines with programmability to optimize power vs. performance.
- Solderless compression mount for 112G PAM4
- 1.6Tbit/s Ethernet PHY on 5nm for cloud data centres
- New timing solutions for 56G/112G SerDes clocking
- Adaptable platform targets network and cloud acceleration
“For the 56G generation we introduced the industry’s first terabit PHY, META-DX1, and now we have followed with an equally transformative 112G solution that delivers the capabilities system developers need to solve today’s new challenges posed by cloud data centers, 5G networking, and AI/ML compute scale-out,” said Babak Samimi, vice president for Microchip’s communications business unit. “By delivering up to 1.6T of bandwidth within a low-power architecture and in the smallest footprint, the META-DX2L PHY doubles the bandwidth of previous solutions on the market while establishing a new level of power efficiency.”
A complete Software Development Kit (SDK) for the new device with hitless upgrade and warm restart capabilities is compatible with the field-proven META-DX1 SDK
Microchip provides a full set of design-in collateral, reference designs, and evaluation boards to support customers building systems with META-DX2L devices. Other devices have been pre-validated for use with the META-DX2L PHY, including PolarFire FPGAs, ZL30632 high-performance PLL, oscillators and voltage regulators.
Initial PM6200 META-DX2L devices are expected to sample during the fourth calendar quarter of 2021.
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