Compression boost for high speed JTAG

October 21, 2021 // By Nick Flaherty
Compression boost for high speed JTAG
XJFlash uses compression to verify 256Mbit test streams in 5.4s

XJTAG in Cambridge has launched an enhanced version of its in-system flash programmer that uses the JTAG interface to connect to the target board.

The  XJFlash software already provides rapid erase and programming, but by adding compression to its data transfer algorithm, the verify times are now also shorter. 256 Mbit can now be verified in 5.4 seconds, depending on the circuit and combining this with its rapid erase and program cycles makes XJFlash significantly faster than other programmers.

XJFlash can be used for Xilinx Zynq UltraScale+ and Zynq-7000 SPI flash programming, as well as with a wide range of FPGAs from Intel/Altera, Lattice, and Microsemi/Actel.

The XJTAG products use IEEE Std.1149.x (JTAG boundary scan) to enable engineers to debug, test, and program electronic circuits quickly and easily. This can significantly shorten the electronic design, development and manufacturing processes.

Production lines also benefit from XJFlash’s rapid erase cycle. Repaired boards can be passed down the line along with new ones without wasting time erasing already-empty memories. XJFlash checks the existing contents, only erasing blocks it finds aren’t empty and can take an empty 256 Mbit flash through the erase step in under 4s, a potential saving of up to 94 percent.

The latest version of XJFlash can program and verify a 256 Mbit flash in 42s, and only needs 7s for a 32 Mbit device (all figures dependent on the circuit implementation).

XJFlash can be used as part of an XJRunner boundary scan test project without needing an additional licence, or it can be used for a separate programming-only stage.

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