Constraints and clock domain crossing sign-off at full-chip level

July 19, 2019 //By Julien Happich
clock domain
EDA tool vendor Cadence Design Systems has released the Conformal Litmus solution, a tool that provides constraints sign-off and clock domain crossing (CDC) sign-off, reducing overall design cycle times and enhancing the quality of silicon in complex SoC designs.

The Conformal Litmus provides designers with 100% sign-off timer accuracy and up to 10X faster turnaround time versus the previous generation solution, claims the company.

Conformal Litmus integrates a sign-off static timer, allowing the tool to accurately model the design and the constraints using the same interpretation as the company’s Tempus Timing Sign-off Solution, providing customers with 100% sign-off accuracy at the register-transfer level (RTL).
The CDC structural sign-off verifies structural correctness of CDC in the design from early RTL through implementation flows. Smart analysis and reporting features provide rapid sign-off capabilities, potentially saving weeks to months in the design schedule.
The constraints sign-off checks for correctness and completeness of constraints at the block level and lets users perform hierarchical block versus top consistency checks at the SoC integration level. What’s more, verification can be parallelized across multiple cores, delivering up to 10X faster turnaround time on SoC designs.
Cadence –

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