The CORE-V Chassis will see a CV64A 64-bit core running alongside a CV32E 32-bit coprocessor core.
Based on the proven NXP iMX platform, the resulting CORE-V Chassis evaluation SoC will also feature 3D and 2D GPUs, MIPI-DSI and CSI display and camera I/O, hardware security blocks, PCIe connectivity, a GigE MAC, USB 2.0 interfaces, support for (LP)DDR4, and multiple SDIO interfaces, along with a wide range of further peripheral blocks.
The 64-bit CV64A core in the CORE-V Chassis is based on the RV64GC RISC-V core IP, originally developed as part of the PULP Platform at the University of ETH Zurich. Optimized for performance, the CV64A core will be capable of clock frequencies of 1.5GHz and alongside the CV64A, is a highly capable CV32E coprocessor core based on the RV32IMFCXpulp RISC-V core IP, also from the University of ETH Zurich.
"NXP is thrilled to be a key contributor to the CORE-V Chassis project leveraging our world class iMX platform,” said Rob Oshana, Chairman of the Board at OpenHW Group and VP Software Engineering at NXP. “We see the CORE-V Chassis project as a natural evolution towards enabling high volume production of OpenHW Group open-source RISC-V cores."
OpenHW Group President and CEO, Rick O’Connor, stated that “The CORE-V Chassis project will help validate that serious silicon development is possible utilizing the ethos of open-source hardware, IP and tools. With the tape out of a functional evaluation SoC during the 2nd half of 2020, we will demonstrate that the open hardware mindset is as capable and dependable as any of today’s closed-source alternatives.”
Once completed, the CORE-V Chassis is earmarked to form the basis of further multi-core evaluation SoCs. Supported by members of the OpenHW Group, the CORE-V Chassis announcement is an open call for industry participation in this ambitious project. OpenHW Group welcomes organisations that want to get involved and help shape the direction of the CORE-V Chassis initiative.
OpenHW Group -