Pixilica in the US has worked with the RV64X to propose a new set of graphics instructions designed for 3D graphics and media processing in a fused CPU-GPU ISA, creating an open source reference implementation for FPGAs.
The RV64X Reference Implementation includes an Instruction/Data SRAM Cache (32KB), a Microcode SRAM(8KB), a Dual Function Instruction Decoder, an Hardwired implementing RV32V and X, a Micro-coded Instruction Decoder for custom ISA, a Quad Vector ALU (32 bits/ALU – fixed/float), a 136-bit Register Files (1K elements), a Special Function Unit, a Texture Unit, and a Configurable local Frame Buffer.
The implementation is designed to be flexible enough so that it can implement custom pipeline stages, custom geometry/pixel/frame buffer stages, custom tessellators, and custom instancing operations. This implementation is optimized to be small and area-efficient with custom programmability and extensibility.
This is one of the strengths of the RISC-V eco-system, says Roddy Urquhart, senior marketing director at Europena tool developer Codasip.
“The RV64X GPU is a fantastic win for the R5 ecosystem,” he said. “If you are going to create a domain-specific processor, one of the key activities is to choose an instruction set architecture (ISA) that matches your software needs,” said Roddy Urqhart at Codasip
“Some companies have created their instruction sets from scratch, but if you have such an ISA, a penalty may be the costs of porting software. Today, the RISC-V open ISA can provide an excellent starting point and a software ecosystem,” he said.
The RISC-V ISA is designed in a modular way that allows processor designers to add not only any of the standard extensions, but also to create their own custom instructions while keeping full RISC-V-compliance.
He points to the base ISA of RISC-V (RV32I) with just 47 instructions. Using this base set is easier than creating proprietary instructions with similar functionality, as well as meaning that software is already available from the RISC-V ecosystem.
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