Digging EDA's big data to speed up chip verification and tape-out: Page 3 of 3

December 15, 2017 //By Julien Happich
Digging EDA's big data to speed up chip verification and tape-out
Founded in 2003 by seasoned EDA veterans, California-based IC Manage made a business out of providing an efficient design and IP management platform for companies to collaborate on single and multi-site designs, supporting and tracking the design data exchange between project managers, IP owners, chip designers, and verification teams.

Talking about the Big Data Labs platform of which Envision VA is the first product, Drako noted that by having provided such analytics for customers during a number of years, the company had realized that many other tools could benefit the semiconductor industry based on big data analytics.

"What we mostly envision is that we'll partner with semiconductor companies that have specific problems and figure out how to solve these problems, then create tools that would meet their precise needs, customizable for others to use.

"We could also partner with EDA companies. We work with all the tools from all the top EDA vendors, our solution is an overlay on top of these tools, so you can see the design progress for many different aspects of a chip" Drako says.

Asked if this sort of data analytics could be performed horizontally across multiple chip designs from different companies, blending in machine learning to extract yet to be discovered patterns of success or failure, the CEO doesn't see it as something likely to happen in the very secretive world of IP design.

"We are not currently looking at, say 200 chip designs over ten years, sifting and trying to find interesting things, we are not doing it between different companies either, and their design methodologies are so different that it may not be fruitful anyway. We are open to try but there are no customer discussions geared toward that, asking to scan all their designs across time and find revealing patterns.

IC Manage - www.icmanage.com


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