Dual 400GbE PHY delivers 100G Serial I/Os and MACsec security

March 10, 2020 //By Julien Happich
400GbE PHY
Marvell has launched what the company claims to be the industry’s first dual 400GbE (Gigabit Ethernet) PHY transceiver with 100GbE serial electrical I/O capabilities, designed to drive next-generation, secured high-density optical infrastructure.

With 100G serial I/Os, the 88X9121P enables the doubling of faceplate bandwidth on datacenter networks while reducing the total power consumption and cost per bit. The new device offers 256-bit MACsec encryption to ensure heightened point-to-point security, Class C compliant precision time protocol (PTP) timestamping for enhanced synchronization and Marvell’s industry-leading 112G PAM4 SerDes technology for high-density 400GbE and 100GbE deployments.
The advent of 100G serial electrical signalling optical modules will allow 1:1 mapping between electrical and optical I/O speeds. This removes the additional circuitry inside 400GbE optical modules to convert from 50G electrical I/Os to 100G per lambda optical I/Os, reducing cost and power. The dual 400GbE MACsec PHY enables interfacing between the current generation of switch ASICs with the next generation of optics and vice versa by supporting translation between 50G PAM4 and 100G PAM4 based implementations of 400GbE, 200GbE and 100GbE.
Marvell - www.marvell.com


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