European processor project shows shift to RISC-V

December 23, 2021 // By Nick Flaherty
European processor project shows shift to RISC-V
The RTL of the Rhea chip from the European Processor Initiative includes 29 RISC-V cores as the second phase starts in January

The European Processor Initiative (EPI) has successfully completed its first three-year phase, delivering multicore chip designs for supercomputers and automotive

The project highlights a shift away from ARM to RISC-V iin the Rhea general-purpose processor, a RISC-V accelerator proof of concept and embedded high-performance microcontroller for automotive applications.

The project has 28 partners from 10 European countries aiming to make the EU achieve independence in high-performance computing (HPC) chip technologies. 

The successful completion of the first phase, SGA1, paves the way for the second instalment of the project, which kicks off in January 2022. 

The initial design of the General-Purpose Processor (GPP), called Rhea, had 72 ARM Zeus processors described to the Linley Conference.

French Supercomputer maker Atos is the lead partner of the General-Purpose Processor (GPP) stream, working with SiPearl. They defined the architectural specifications of Rhea, which now has 29 cores using the RISC-V open instruction set architecture and is at the RTL level in emulation, rathe than an implementation in silicon. The design is intended for use in a supercomputer design in 2023.

“With 29 RISC-V cores, the Arm Neoverse V1 architecture used by SiPearl to design Rhea will offer an effective, scalable and customisable solution for HPC applications,” said the project. “Architectural decisions were taken following a co-design methodology and by analysing the performance of advanced intellectual property (IP) blocks. A scalable network-on-chip (NoC) to enable high-frequency, high-bandwidth data transfers between cores, accelerators, input / output (IO) and shared memory resources was also optimised by SiPearl.”

“We are proud of our success in designing a powerful GPP leveraging cutting edge technologies and IPs built and deployed exclusively by European universities and industrial leaders. We are confident that we will soon demonstrate the instrumental role of this GPP in enabling a European exascale computing machine, the next breakthrough in the HPC domain the world is expecting,” said Stream Leader Emmanuel Ego at Atos.

“With the release of the Rhea processor, we will all contribute to ensure European sovereignty in HPC applications such as personalised medicine, climate modelling, and energy management.” – said Philippe Notton, founder and CEO of SiPearl.

Next: HBM2E memory architecture

Picture: 
The original timescale for the EPI project

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