First steps to European multicore RISC-V chip for space: Page 2 of 2

November 16, 2020 // By Nick Flaherty
First steps to European multicore RISC-V chip for space
The De-risc project has shown the first milestones for a purely European multicore RISC-V processor for satellite, spavce and HAPS designs

and/or lossless data compression.

This allows the assessment of both time-critical and cybersecurity aspects of the platform, as well as overall performance and data throughput. The test application will be configurable, e.g. in data size, to focus on each of those aspects, but the low-level communication protocol will not be included. In addition, synthetic benchmarks and stress applications will be used to assess the sensitivity of the platform to timing interference

The project is using the Stratobus project by Thales Alenia Space, a stratospheric HAPS balloon that has both space and aviation requirements.

The next software tasks include porting of RTEMS, a free open source real-time operating system, as guest operating system of XtratuM XNG, and the upgrade of the software development tools to support XNG and LithOS on NOEL-V.

derisc-project.eu

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