FPGA-based SoC prototyping, at up to 100 MHz system clock: Page 2 of 2

September 16, 2015 //By Graham Prophet
FPGA-based SoC prototyping, at up to 100 MHz system clock
Synopys says its HAPS-80 FPGA-based prototyping system, with ProtoCompiler preparation software, can yield 100 MHz system performance in a multi-FPGA environment; ProtoCompiler software, dedicated to the HAPS systems, automates design partitioning to reduce time to first prototype to less than two weeks on average.
Xilinx comments, from the company’s Hanneke Krekels, director of test, measurement and emulation market business, “Synopsys has used six prior generations of Xilinx FPGA devices and is a long-term business partner of Xilinx for FPGA-based prototyping. Synopsys’ tightly integrated hardware and software HAPS FPGA-based prototyping solution is positioned to deliver the highest performance and capability from the Virtex UltraScale VU440 device.”

Synopsys’ John Koeter, vice president of marketing for IP and prototyping, concludes, “The new HAPS-80 series addresses SoC designers’ pain points in the areas of performance, scalability, time to first prototype and debug, while maintaining interoperability with HAPS-70 systems... the combination of HAPS hardware and ProtoCompiler software delivers the fastest time to first prototype with the highest performance to accelerate software development, hardware/software integration and system validation of large SoC and GPU designs.”

Synopsys; www.synopsys.com

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