FPGA cores offered for TSMC's 40ULP process

August 29, 2016 //By Peter Clarke
FPGA cores offered for TSMC's 40ULP process
Flex Logix Technologies Inc. (Mountain View, Calif.) has completed the design of a family of reconfigurable FPGA cores for implementation in TSMC's 40nm ultra-low power manufacturing process.

Flex Logix' business model is that of licensing the technology to customers that want to include FPGA fabric in their SoCs and standard products.

Silicon for the EFLX family for 40ULP is in fabrication at TSMC and is expected to be validated during 4Q16. It is being aimed at providing reconfigurable RTL for microcontrollers and SoCs used in the Internet of Things. The inclusion of FPGA fabric can give a single die multiple functions and hardware accelerator functions and allows chips to be updated or changed at any time after fabrication, even in-system

Flex Logix, a startup founded in 2014, pitched its first FPGA fabric at system-on-chip (SoC) design on the 28nm HPM process launching in 2015 (see Put FPGAs in your SoCs ). The latest family back fills the family and addresses a broader potential customer base.

Flex Logix’ is offering both  logic variant and DSP variant of its fabric on TSMC 40ULP and are specified for operation at both 1.1V and 0.9V with state retention down to 0.5V. The EFLX-100 IP cores/arrays in TSMC 40ULP require only 5 metal layers and support multiple clocks

EFLX-100 Logic IP core: 120 LUTs – each LUT is dual 4-input look-up-tables with dual flip flops – with reconfigurable interconnect, clocks, configuration logic/memory and 304 I/O in 0.13 square millimeters. Each is available in five different threshold voltage (VT) combinations to fit customers’ designs and power/performance trade-offs. EFLX-100 DSP IP core: 88 LUTs and two MACs (22bit by 22bit multipler with pre-adder and 48-bit post-adder), with the same I/O and area as the EFLX-100 Logic IP core.  This is also available in five different VT combinations.

The EFLX-100 IP cores can be arrayed to make larger arrays up to 5 by 5 with any combination of Logic and DSP IP cores inter-mixed.  This means that there are 25 different possible array sizes/dimensions from 120 LUTs to 3000 LUTs; and hundreds of unique arrays

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