FPGA power system management

May 21, 2020 //By Pinkesh Sachdev
FPGA
Field-programmable gate arrays (FPGAs) trace their origins back to the 1980s, evolving from programmable logic devices (PLDs). Since then, FPGA resources, speed, and efficiency have improved rapidly, making FPGAs the go-to solution for a wide variety of computing and processing applications, especially when production volume doesn’t justify application-specific integrated circuit (ASIC) development costs.

FPGAs have advanced to such an extent that they’ve also found homes in large-scale deployments. For instance, after successfully speeding up the Bing search engine with FPGAs in a 2013 pilot program, Microsoft expanded FPGA-equipped server usage to its cloud data centers.

 

FPGA power system requirements

FPGAs require a few different low voltage supply rails, each with its own voltage and current specification, to power their internal core logic, I/O circuits, auxiliary logic, transceivers, and memory. These rails may need to turn on and turn off in a specific sequence to avoid damaging the FPGA. Point-of-load (POL) regulators step down the board’s higher input supply voltage to the multiple lower rail voltages required by the FPGA. Switching regulators are used as POL regulators when power conversion efficiency is paramount, whereas linear regulators—for example, low dropout (LDO) regulators—are employed for noise-sensitive circuits such as PLLs and transceivers.


Fig. 1: One possible FPGA power tree: a high voltage input
supply (for example, 12 V, 24 V, or 48 V) is stepped down to
an intermediate voltage bus feeding the POL regulators that
power the FPGA.

Typical board input voltages are 5 V, 12 V, 24 V, and 48 V, while FPGA rail voltages range from below 1 V to around 3 V. For high input voltages (12 V, 24 V, 48 V), an extra step-down may be needed to generate an intermediate voltage bus that feeds the POL regulators (see Figure 1). Among the FPGA rails, the core supply requires the lowest voltage (around or below 1 V) and highest accuracy (±3% or better), with current levels in the tens of amperes depending on FPGA resource utilization.

To prevent logic errors, the supply variation needs to be limited to tens of millivolts, as dictated by the FPGA rail tolerance specification, not just under dc conditions but also during FPGA current transients. The worse the power supply’s dc accuracy, the more bypass capacitance is needed to maintain an acceptable supply voltage under transient conditions. For example, assume a ±3% core voltage tolerance specification. Using a ±1% accurate dc supply leaves a good ±2% allowance for transients. On the other hand, a less accurate ±2% dc supply leaves less room (±1%) for transients, requiring more bypass capacitance than the previous case.


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