Tweaking or trimming of the FPGA supply voltage level around the default setpoint is required for last-minute design changes, design reuse in another application, board margin testing, and dynamically optimizing system power consumption during development or field operation. Soldering in different resistors in the supply’s
feedback network isn’t the quickest or most feasible solution for such situations. One method to achieve voltage trimming is with a digital-to-analog converter (DAC) driving the feedback network of a voltage regulator (see Figure 2). Software code needs to be written for the trim routine to obtain supply voltage measurement data from an analog-to-digital converter (ADC), to compute the correct DAC code, and then slowly adjust the DAC output to the computed code for smoothly ramping the supply voltage, without glitches or overshoots, to the target level. This trim routine needs to be repeated over time to ensure that the supply doesn’t walk away from the target voltage due to components drifting with time or temperature.
Monitoring FPGA supply voltages, currents, and faults is essential to understanding system health and power consumption under different scenarios because the FPGA is the brain of the electronic system. Such an understanding, coupled with trimming capability, avoids designing supplies for the worst case, saving cost and power. Moreover, an upcoming system malfunction could show up as an abnormal trend in FPGA power consumption, alerting the host controller or service staff before the board or system goes down.