FPGA power system management: Page 3 of 6

May 21, 2020 //By Pinkesh Sachdev
Field-programmable gate arrays (FPGAs) trace their origins back to the 1980s, evolving from programmable logic devices (PLDs). Since then, FPGA resources, speed, and efficiency have improved rapidly, making FPGAs the go-to solution for a wide variety of computing and processing applications, especially when production volume doesn’t justify application-specific integrated circuit (ASIC) development costs.

Voltage monitoring requires ADCs, whereas current monitoring also requires level-shift circuits to translate the high-side current sense voltage to a ground-referenced voltage; for example, with a transconductance amplifier, as shown in Figure 3.

Fig. 3: One possible discrete circuit for monitoring POL
supply output voltage, current, and power.

One’s head may be spinning after reading this long laundry list of requirements although we have not discussed fault management. What should happen when a POL output goes undervoltage or overvoltage—that is, outside the valid voltage window? Should only the faulting supply be turned off, or should other supplies be turned off too? How does one debug a fault that has shut down the board?

As one can see, managing an FPGA’s power system can become complicated very quickly, distracting from the essential FPGA application. Remember that the FPGA’s power tree is just a portion of the overall power system on a digital processing board. Most of the above requirements also apply to other digital devices such as ASICs, DSPs, GPUs, SoCs, and microprocessors. What is needed is a power system management solution that is simple, scalable, and flexible.

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.