FPGA power system management: Page 4 of 6

May 21, 2020 //By Pinkesh Sachdev
FPGA
Field-programmable gate arrays (FPGAs) trace their origins back to the 1980s, evolving from programmable logic devices (PLDs). Since then, FPGA resources, speed, and efficiency have improved rapidly, making FPGAs the go-to solution for a wide variety of computing and processing applications, especially when production volume doesn’t justify application-specific integrated circuit (ASIC) development costs.

Digital power system management

Analog Devices provides a portfolio of digital power system management (DPSM) devices to deal with the complex power systems found on digital processing boards. DPSM devices are available with and without integrated dc-to-dc conversion to either replace POL regulators or work with existing POL regulators. Power system managers—that is, without dc-to-dc conversion—add digital monitoring and control to any existing analog power system, whether made up of switchers or LDO regulators. A single device such as the LTC2980 trims, margins, monitors, sequences, supervises, fault logs, and fault manages 16 POL regulators. Differing channel-count devices (2, 4, 8, or 16 channels) can be mixed and matched to manage hundreds of rails. The 2-channel LTC2972 is the latest addition to this portfolio, providing a simple introductory solution for monitoring and controlling the two most critical rails in such a power system; for example, the FPGA core and auxiliary rails.

 

2-channel power system manager


Fig. 4: LTC2972, a 2-channel power system manager with
intermediate bus energy monitoring and POL output power
monitoring.

The LTC2972 is a 2-channel power system manager, adding comprehensive software-based monitoring, control, and black box fault recording to the power systems of FPGA, ASIC, and processor boards, accelerating time to market, enhancing system reliability, and optimizing board energy consumption (Figure 4).

POL supply output voltages are trimmed, margined, and monitored using a best-in-class 16-bit ADC with 0.25% total unadjusted error (TUE), improving board yields and long-term performance. The ability to tighten POL output voltage to ±0.25% accuracy leaves plenty of room for it to move during load transients (±2.75% for a ±3% FPGA rail specification), significantly reducing needed bypass capacitance and freeing up board space. Supply output currents are measured using a sense resistor, inductor DCR, or the IMON output of a power supply. The voltage and current measurements are multiplied internally to provide a convenient POL power output reading.


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