Future trends for verification: Page 4 of 4

November 13, 2020 //By Nick Flaherty
Future trends for verification
Martin Barnasconi from NXP and Alex Rath from Infineon Technologies talk to Nick Flaherty about the challenges for the verification industry revealed at DVcon Europe, from UVM and Python to digital twins and instrumentation.


Encouraging just one language for verification is also not a viable way forward for the combination of hardware, software and system verification, despite the advantages to engineers and tool developers.  

“What we have also seen is the need for multi-language frameworks,” said Barnasconi. “Many teams are using System Verilog, VHDL and SystemC are driven from the hardware world so we are dealing with a multi-language environment and the software world is using other languages so we have an interesting challenge.”

“I don’t think we will need to consolidate into a single language but we need to come up with a way those approaches can talk to each other so is all about interfaces and communication, and there an Accelera working group on that. We need this is the verification space. We have languages that are better at the system level and these need to be integrated and have clear definitions of how the interfaces should be done. The good news is that many standards have defined transaction levels, and back to digital twin these are defined, so we are zooming in on how different entities talk to each other and we need to talk to these.”

“I see users using Python and vendor support so we are entering a new era in that sense – it is a language that is recognised and we need to incorporate it – it is a valuable asset and we need to find the right mechanism, not just a binding layer. You need to work out how Python components can work with SystemC components,” he said.

“Python is probably THE language in academia so all the freshers speakers Python,” said Rath. “Who speaks VHDL any more coming out of university? Everything coming for AI is typically built in Python so those people joining the semiconductor industry or the EDA industry its natural for them to build stuff in Python, so we will see that more as an interface to design tools.”

All of these issues need more connection between the different parts of the industry, they say.

“At DVcon we aim to give a platform for engineers, not just verification, we want more system design and software to address these kinds of topics,” said Barnasconi. “Verification needs to connect to the software flow, hardware prototyping, so we need to put this into the design eco-system. That takes time, to connect communities and industries together, and one of the high level ambitions is to have the verification and design communities to interact.”   


Related articles 

Other articles on eeNews Europe

Verification engineers Martin Barnasconi from NXP and Alex Rath from Infineon Technologies

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.