The port of the INtegrity RTOS to RISC-V allows electronics manufacturers worldwide can confidently build and deploy safety and security-critical, high performant RISC-V systems with the same software that is used in critical systems found in cars, aircraft, trains, secure phones, and surgical devices.
The Integrity RTOS is integrated with RISC-V processor solutions including hardware reference boards from Microchip and SiFive, along with processor intellectual property (IP) from SiFive, a leading RISC-V IP provider. This support provides the path to enabling device manufacturers to reduce the time, cost and complexity of developing and deploying critical software for automotive, military, IoT and industrial solutions based on the new RISC-V processor architecture.
Integrity is based on a separation kernel architecture that provides resource guarantees, hard real-time determinism and was designed from the beginning to achieve maximum security and safety. The associated Multi debugger with C/C++ compilers and analysis tools is purpose-built to find even the most difficult bugs on complex RISC-V SoCs comprised of multiple heterogenous cores where the RISC-V core is either the main general-purpose CPU or a secondary special-purpose acceleration core alongside a CPU, such as an ARM core.
The compiler has support for a comprehensive list of ISA modules with both 32-bit and 64-bit RISC-V architectures and debugger support for custom Instructions.
A popular feature of the open RISC-V architecture is that users can incorporate their own custom instructions into their design. The Green Hills compilers offer an easy-to-learn and use interface for adding new instructions into the compiler, assembler, MULTI debugger, and instruction set simulator. The compiler supports the modular nature of the RISC-V architecture by allowing the user to choose exactly the instruction set modules they would like to compiler their code for. Supported instruction set modules are:
- "I" Core integer set of instructions
- "A" Atomic instructions
- "M" Multiply and divide instructions
- "C" Compressed Instructions
- "F" Single precision floating point instructions
- "D" Double precision floating point instructions
RISC-V also includes a separate privileged instruction set specification and these privileged instructions are supported. Pre-built runtime libraries are provided for compatibility with all of these configurations.
“As a leading supplier of SoC FPGAs that offer exceptional reliability, the best security and 30-50 percent lower power than competing devices, having Green Hills Software bring its full safety and security portfolio to customer applications using PolarFire SoC is a significant milestone for the Mi-V RISC-V ecosystem and to the larger RISC-V ecosystem,” said Tim Morin, Technical Fellow and Marketing at Microchip Technology. “The addition of safe and secure software tools will greatly enable the ability of our joint clients to innovate with a free and open ISA.”
“The integration of safety and security-critical RTOS, INTEGRITY, into SiFive HiFive products is an exciting step forward for the RISC-V and SiFive ecosystem,” said Dr. Yunsup Lee, CTO, SiFive, and co-inventor of RISC-V. “The market for trusted RISC-V-based solutions is growing rapidly and the support of Green Hills Software’s deep experience will create opportunities for the SiFive Performance, Intelligence, and Essential families of RISC-V-based IP.”
The µ-velOSity RTOS is already ported to RISC-V, and Multi works with the Green Hills Probe v4 for multicore hardware bring-up, low-level debugging, and trace-powered analysis tools.
The Integrity RTOS, Multi IDE and the Green Hills Probe are available today to early-access customers for the Microchip PolarFire Icicle Kit and the SiFive HiFive Unmatched board.
- GHS Integrity OS support for Renesas' 3rd-gen R-Car H3 SoC
- ARM and GHS partner on functional safety
- Green Hills teams with MathWorks for embedded code toolbox
- Integrity RTOS meets requirements of ISO/SAE 21434
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