Microchip Technology has an HLS design workflow to its PolarFire FPGA families that allows C++ algorithms to be directly translated to FPGA-optimized Register Transfer Level (RTL) code.
A large majority of edge compute, computer vision and industrial control algorithms are developed natively in C++ by developers with little or no knowledge of underlying FPGA hardware. The SmartHLS toolflow is based on the open-source Eclipse integrated development environment and uses the C++ code to generate an HDL IP component that can be integrated into Microchip’s Libero SmartDesign projects. This enables engineers to describe hardware behaviour at a higher level of abstraction than is possible with traditional FPGA RTL tools.
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“SmartHLS enhances our Libero SoC design tool suite and makes the vast benefits of our award-winning mid-range PolarFire and PolarFire SoC platforms accessible to a diverse community of algorithm developers without them having to become FPGA hardware experts,” said Bruce Weyer, vice president of Microchip’s FPGA business unit. “Together with our VectorBlox Neural Network Software Development Kit these tools will greatly improve designers’ productivity in creating cutting-edge solutions using C/C++ based algorithms for applications such as embedded vision, machine learning, motor control and industrial automation using FPGA-based hardware accelerators.”
The SmartHLS tool also includes a multi-threading Application Programming Interface (API) that executes hardware instructions concurrently and simplifies the expression of complex hardware parallelism in the FPGA design.
As a result the tool requires up to 10 times fewer lines of code than an equivalent RTL design, with the resultant code being easier to read, understand, test, debug and verify. The tool also simplifies exploration of hardware microarchitecture design trade-offs and enables a developer’s pre-existing C++ software implementations to now be used with PolarFire FPGAs and FPGA SoCs.
PolarFire FPGAs and FPGA SoCs as well as SmartFusion 2 and IGLOO 2 FPGA are supported by the SmartHLS v2021.2 tool, which is available on the Microchip website. It is part of the recently released Libero SoC V2021.2 design suite and can also be used as stand-alone software.
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