Hybrid co-verification platform offers automated FPGA partitioning software

October 18, 2019 // By Julien Happich
verification platform
Aldec announced it has developed a powerful hybrid co-emulation platform for large ASIC and SOC designs using its HES-US-440 hardware emulation system and an Aldec TySOM-3 embedded system board featuring a Xilinx Zynq Ultrascale+ FPGA.

An FMC Host2Host bridge between the two Aldec products allows the TySOM board to share the ARM cores with the HES, meaning the software team members can prototype on fast clock-speed hardware and benefit from fast system boot-up (minutes instead of hours).

The company has also demonstrated automatic FPGA partitioning for its HES-DVM tool; the company’s fully automated and scalable hybrid verification environment for SoC and ASIC designs. Traditionally, and subject to design complexity and constraints, the manual partitioning of multiple FPGAs used for prototyping can take days, or even weeks, whereas HES-DVM can perform the task in minutes.

Aldec- www.aldec.com

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