Technology Association. The xSPI standard defines requirements for the compatibility of high-performance x8 serial interfaces, including read and write commands, electrical characteristics, signalling protocols for command and data transfers, and a standard pin-out in a Ball Grid Array (BGA) footprint. The inclusion of the HyperBus interface in the JEDEC xSPI standard simplifies designing in HyperBus-based memories and provides more flexibility to system designers to implement instant-on functionality in automotive, industrial and IoT applications.
Cypress was the first NOR flash memory supplier to identify the market requirement for a high-speed, 8-bit bus and introduced the HyperBus interface in 2014. The company's HyperBus-based memories include high-density HyperFlash NOR Flash devices with the bandwidth required for the
highest-performance embedded systems and high-speed HyperRAM self-refresh Dynamic RAM (DRAM) devices for systems requiring expanded scratchpad memory.
The 12-pin Cypress HyperBus interface consists of an 8-pin address/data bus, a differential clock (2 signals), one chip select and a read data strobe for the controller, reducing the overall cost of a system.
Cypress - www.cypress.com