IBM pledges nanotube transistor by 2020 or bust

July 04, 2014 //By R. Colin Johnson
IBM pledges nanotube transistor by 2020 or bust
For over two decades IBM has tried nearly every possible way to a make a tiny 1.4-nanometer carbon nanotube the successor to the silicon transistor channel.
Today the smallest silicon transistors are already achieving atomic limits -- a 4-nanometer silicon transistor channel, for instance, would consist of about 20 atoms. To go to the next silicon generation, all sorts of imperfections and uneven doping problems are facing the further downsized silicon transistors.

If IBM, or others -- in fact China is now leading in nanotube research -- can perfect the 1.4-nanometer transistor channel, then Moore's law can keeping marching forward a little while longer. If not, a whole new paradigm may have to be invented.

Relatively recently, the nanotube transistor guru, IBM Fellow Phaedon Avouris, found greener pastures to explore in plasmonics and photonics. The nanotube team is now led by Wilfried Haensch at the T.J. Watson research lab of Yorktown Heights, N.Y. Haensch is facing the same problem that Avouris has been facing, that of how to position such impossibly small components into nice neat straight lines for transistor canals. He has a few new tricks up his sleeve, some put there by James Hannon, head of IBM's molecular assemblies and devices group.

The source and drain electrodes cover the carbon nanotubes channel, all controlled by the same local back gate.(Source: IBM)
The source and drain electrodes cover the carbon nanotubes channel, all controlled by the same local back gate.
(Source: IBM)

One new idea is not to depend on just a single nanotube, but to use multiple nanotubes for a transistor channel, hoping that at least a few work. In simulations, they have lined up six relatively parallel 1.4-nanometer-wide and 30-nanometer-long nanotubes with a generous spacing of 8-nanometers between them.

The ends are embedded in the source and drain of the nanotube, leaving 10-nanometer channels suspended over the gate electrode at the bottom of the stack. Their next simulation will be to label the substrate and nanotubes chemically for correct alignment, then strip away the chemicals for a real finished chip -- an IBM Power7.

Haensch tells EE Times:

    The six-tube device structure came out of complex optimization process that models the performance of an entire microprocessor, in this case an IBM Power7 chip. The optimizer varies the layout of the device, including the wiring, and predicts the system performance.

The International Technology Roadmap for Semiconductors (ITRS) calls for the 5-nanometer node to be reached by 2019, so IBM has set is goal for nanotube transistors by 2020.

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