- The device will incorporate 5 to 6 CNTs [per channel]. The CNTs will have a diameter around 1.4 nanometers. The diameter is chosen to give the desired band gap. In order to achieve a performance advantage over silicon, the device must be small. The model suggests that we need a nanotube pitch (CNT-CNT distance) of about 8 nanometers. The channel (or gate) length (Lg) will be about 10 nanometers, with source (S) and drain (D) contacts also about 10 nanometers long. LBG is the local bottom gate. That is the electrode that controls the channel conduction. We have already built devices with less than 10-nanometer channel lengths. The 10 nanometer CNT pitch is difficult to achieve due to the limitations of patterning methods, but we have published results with 200-nanometer CNT pitch. We have also built multi-CNT devices (with 2, 3, 4, and 6 CNTs). As expected, the current is larger, but the variability of the devices is reduced due to the averaging effect of having multiple CNTs in the channel.
According to Haensch, there are several hurdles at need to be surmounted to meet the 2020 dead line, not least of which is separating the semiconducting from metallic nanotubes, which has been an enduring problem from the beginning over two decades ago. He tells EE Times:
- The major hurdles for a successful CNT VLSI technology [are] placement control and degree of purity of the carbon nanotubes. To meet both challenges, different approaches are pursued. IBM favors [depositing] a highly purified population of CNTs on a wafer at predetermined locations defined by chemical markers. This way, randomness due to elimination of metallic CNTs is significantly minimized, and the distribution of the CNTs across the wafer can be very well controlled.
IBM is committed to try to meet the 2020 deadline, but admits that all major hurdles much be surmounted to keep the project alive after 2020. Otherwise other techniques such as spintronics, which is less mature today, will likely overtake nanotube research then.
— R. Colin Johnson, Advanced Technology Editor, EE Times
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